Мучаем 5576ХС4Т - часть 'h27 - PNG и коды коррекции ошибок CRC32

 89  50  4e  47  0d  0a  1a  0a

\211   P   N   G  \r  \n \032 \n

00 00 00 0d

x^32+x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x+1

//-----------------------------------------------------------------------------
// Copyright (C) 2009 OutputLogic.com 
// This source file may be used and distributed without restriction 
// provided that this copyright statement is not removed from the file 
// and that any derivative work contains the original copyright notice 
// and the associated disclaimer. 
// 
// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS 
// OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED 
// WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. 
//-----------------------------------------------------------------------------
// CRC module for data[0:0] ,   crc[31:0]=1+x^1+x^2+x^4+x^5+x^7+x^8+x^10+x^11+x^12+x^16+x^22+x^23+x^26+x^32;
//-----------------------------------------------------------------------------
module crc(
  input [0:0] data_in,
  input crc_en,
  output [31:0] crc_out,
  input rst,
  input clk);

  reg [31:0] lfsr_q,lfsr_c;

  assign crc_out = lfsr_q;

  always @(*) begin
    lfsr_c[0] = lfsr_q[31] ^ data_in[0];
    lfsr_c[1] = lfsr_q[0] ^ lfsr_q[31] ^ data_in[0];
    lfsr_c[2] = lfsr_q[1] ^ lfsr_q[31] ^ data_in[0];
    lfsr_c[3] = lfsr_q[2];
    lfsr_c[4] = lfsr_q[3] ^ lfsr_q[31] ^ data_in[0];
    lfsr_c[5] = lfsr_q[4] ^ lfsr_q[31] ^ data_in[0];
    lfsr_c[6] = lfsr_q[5];
    lfsr_c[7] = lfsr_q[6] ^ lfsr_q[31] ^ data_in[0];
    lfsr_c[8] = lfsr_q[7] ^ lfsr_q[31] ^ data_in[0];
    lfsr_c[9] = lfsr_q[8];
    lfsr_c[10] = lfsr_q[9] ^ lfsr_q[31] ^ data_in[0];
    lfsr_c[11] = lfsr_q[10] ^ lfsr_q[31] ^ data_in[0];
    lfsr_c[12] = lfsr_q[11] ^ lfsr_q[31] ^ data_in[0];
    lfsr_c[13] = lfsr_q[12];
    lfsr_c[14] = lfsr_q[13];
    lfsr_c[15] = lfsr_q[14];
    lfsr_c[16] = lfsr_q[15] ^ lfsr_q[31] ^ data_in[0];
    lfsr_c[17] = lfsr_q[16];
    lfsr_c[18] = lfsr_q[17];
    lfsr_c[19] = lfsr_q[18];
    lfsr_c[20] = lfsr_q[19];
    lfsr_c[21] = lfsr_q[20];
    lfsr_c[22] = lfsr_q[21] ^ lfsr_q[31] ^ data_in[0];
    lfsr_c[23] = lfsr_q[22] ^ lfsr_q[31] ^ data_in[0];
    lfsr_c[24] = lfsr_q[23];
    lfsr_c[25] = lfsr_q[24];
    lfsr_c[26] = lfsr_q[25] ^ lfsr_q[31] ^ data_in[0];
    lfsr_c[27] = lfsr_q[26];
    lfsr_c[28] = lfsr_q[27];
    lfsr_c[29] = lfsr_q[28];
    lfsr_c[30] = lfsr_q[29];
    lfsr_c[31] = lfsr_q[30];

  end // always

  always @(posedge clk, posedge rst) begin
    if(rst) begin
      lfsr_q <= {32{1'b1}};
    end
    else begin
      lfsr_q <= crc_en ? lfsr_c : lfsr_q;
    end
  end // always
endmodule // crc

//-----------------------------------------------------------------------------
// Copyright (C) 2009 OutputLogic.com 
// This source file may be used and distributed without restriction 
// provided that this copyright statement is not removed from the file 
// and that any derivative work contains the original copyright notice 
// and the associated disclaimer. 
// 
// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS 
// OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED	
// WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. 
//-----------------------------------------------------------------------------
// CRC module for data[0:0] ,   crc[31:0]=1+x^1+x^2+x^4+x^5+x^7+x^8+x^10+x^11+x^12+x^16+x^22+x^23+x^26+x^32;
//-----------------------------------------------------------------------------
module CRC32_by_output_logic(
  input data_in,
  input crc_en,
  input just_shift,
  output [7:0] CRC_byte,
  input rst,
  input clk);

	wire d = (~just_shift) & (data_in ^ CRC[31]);
	
	reg [31:0] CRC;
	
	assign CRC_byte = CRC[7:0];
	
  always @(posedge clk) begin
    if (rst) begin
      CRC <= {32{1'b1}};
    end
    else if (crc_en | just_shift) begin
		CRC[0] <= CRC[31] ^ (data_in & (~just_shift));
		CRC[1] <= CRC[0] ^ d;
		CRC[2] <= CRC[1] ^ d;
		CRC[3] <= CRC[2];
		CRC[4] <= CRC[3] ^ d;
		CRC[5] <= CRC[4] ^ d;
		CRC[6] <= CRC[5];
		CRC[7] <= CRC[6] ^ d;
		CRC[8] <= CRC[7] ^ d;
		CRC[9] <= CRC[8];
		CRC[10] <= CRC[9] ^ d;
		CRC[11] <= CRC[10] ^ d;
		CRC[12] <= CRC[11] ^ d;
		CRC[13] <= CRC[12];
		CRC[14] <= CRC[13];
		CRC[15] <= CRC[14];
		CRC[16] <= CRC[15] ^ d;
		CRC[17] <= CRC[16];
		CRC[18] <= CRC[17];
		CRC[19] <= CRC[18];
		CRC[20] <= CRC[19];
		CRC[21] <= CRC[20];
		CRC[22] <= CRC[21] ^ d;
		CRC[23] <= CRC[22] ^ d;
		CRC[24] <= CRC[23];
		CRC[25] <= CRC[24];
		CRC[26] <= CRC[25] ^ d;
		CRC[27] <= CRC[26];
		CRC[28] <= CRC[27];
		CRC[29] <= CRC[28];
		CRC[30] <= CRC[29];
		CRC[31] <= CRC[30];
    end
  end // always
endmodule // crc

assign CRC_byte = CRC[0:7]; 

//module for transmitting PNG images over UART or another serial protocol.
//To be sensible to series of zeros, it was decided to first initialize CRC with all ones,
//then invert final value once again.
//that's what we do here. Seems like most 'comfortable' place for this operation.
//not to 'overload' CRC module.

module Data_or_CRC_MUX (input [7:0] Data, input [7:0] CRC, input ChooseCRC, output [7:0] Q);

wire [7:0] CRCrev;

	assign CRCrev[0] = CRC[7];
	assign CRCrev[1] = CRC[6];
	assign CRCrev[2] = CRC[5];
	assign CRCrev[3] = CRC[4];
	assign CRCrev[4] = CRC[3];
	assign CRCrev[5] = CRC[2];
	assign CRCrev[6] = CRC[1];
	assign CRCrev[7] = CRC[0];


assign Q = ChooseCRC? ~CRCrev : Data;

endmodule