Продолжаем тормозить (ABS подвела)

//most complicated thing so far. Should support commands:
//NOP (smth else is active) 
//0x80: ACC
//0x81: PM
//0x82: ADD
//0x83: SUB

//0x84: ABS
//0x85: ???
//0x86: ???
//0x87: ???

//0x88: ZACC
//0x89: ???
//0x8A: C
//0x8B: ???

//0x8C: DIV2
//0x8D: ???
//0x8E: ???
//0x8F: ???

//0x90: MUL
//0x91: FMPM
//0x92: FMA
//0x93: FMS

//0x94: MULSU
//0x95: SUFMPM
//0x96: SUFMA
//0x97: SUFMS

//0x98: MULU
//0x99: UFMPM
//0x9A: UFMA
//0x9B: UFMS

//0x9C: SQRD2
//0x9D: SQRPMD2
//0x9E: SQRAD2
//0x9F: SQRSD2

//100xxxxx = ALU commands
//1000xxxx = 'short' commands
//1001xxxx = 'long' commands

//100xxx00 = 'clear ACC'
//100xxx10 = 'add to ACC'
//100xxx11 = 'sub from ACC'
//100xxx01 = 'plus-minus' (depends on PM input)

//100x00xx = 'signed commands'
//100x01xx = 'signed B / unsigned C commands / special command (ABS)'
//100x10xx = 'unsigned commands / special commands (ZAcc, C)'
//100x11xx = 'div2 commands (DIV2, SQRD2, SQRAD2 etc)'

//AccMode = 	000 - load
//		001 - FORBIDDEN
//         	010 - idle
//		011 - clear
//		100 - set -3/2
//		101 - set 2
//		110 - set 3/2
//		111 - set 1/2lsb

//Bmode   =	00 - shift right
//		01 - shift right and invert
//		10 - load 16 bit
//		11 - load AccWidth bit (bypass)

//Cmode   = 	0x - idle
//		10 - shift
//		11 - load
module QuatCoreALUcontrol (input Bypass, input clk, input [7:0] DestAddr, input Csenior, input PM, input [15:0] D,
			output [2:0] AccMode, output cin, output BSigned, output [1:0] Bmode, output [1:0] Cmode, output Sena, output Busy);
							
wire isOurAddr	   = (DestAddr[7:5] == 3'b100);
wire isLongCommand = DestAddr[4];
wire [1:0] PlusMinusMode = DestAddr[1:0];

wire OpSign = PlusMinusMode[0] & (PlusMinusMode[1] | PM); //0 is '+', 1 is '-'
wire isSignedC = (DestAddr[3] == DestAddr[2]);

reg SeniorDataBit = 1'b0;
always @(posedge clk) if (isIdle)
	SeniorDataBit <= D[15];

wire FirstDivSign = OpSign ^ (isLongCommand & isSignedC & (isFirstDiv | MulFirst)) | (SeniorDataBit & (~isLongCommand) & (~DestAddr[3]) & DestAddr[2]);


//first of all, 'state machine'
localparam sIdle = 3'b000;
localparam sDiv2 = 3'b001;
localparam sFirstDiv = 3'b010;
localparam sAdd  = 3'b011;
localparam sMult = 3'b100;

reg [2:0] State = sIdle;


wire isIdle = (State == sIdle);
wire isFirstDiv = (State == sFirstDiv);
wire isDiv2 = (State == sDiv2);
wire isAdd = (State == sAdd);
wire isMult = (State == sMult);

reg MulFirst = 1'b0;
always @(posedge clk)
	MulFirst <= isFirstDiv;

	

//also, 4-bit counter for multiplier
wire finished; //when multiplication is all over
 lpm_counter	counter (
			.clock (clk),
//			.cnt_en (IsIdle),
			.sclr (~isMult),
			.cout (finished) );
  defparam
    counter.lpm_direction = "UP",
    counter.lpm_port_updown = "PORT_UNUSED",
    counter.lpm_type = "LPM_COUNTER",
    counter.lpm_width = 4;


//now combinatorial logic which depends on current state, DestAddr and other inputs
assign AccMode = 	isIdle?	((isOurAddr & (PlusMinusMode == 2'b00))? {1'b1, D[1:0]} : 3'b010) :
			(isFirstDiv | isDiv2)?	{isLongCommand & (PlusMinusMode == 2'b00), 1'b1, (PlusMinusMode == 2'b00)}:
			isAdd?	3'b000:
				{1'b0, ~Csenior, 1'b0};
//in 'clear' commands we either don't care of contents at first step (will clear it anyway),
//or this is ZAcc command which sets one of consts. So we seek for this command
//otherwise AccMode is idle.
					
assign cin = FirstDivSign; //don't care at idle/FirstDiv/Div2, care at sAdd so far

assign BSigned = 	(DestAddr[3:2] != 2'b10); //this row equals fully unsigned operation
							
assign Bmode = 	isIdle? 	{1'b1, Bypass}:
		isFirstDiv?	{1'b0, FirstDivSign} :
				{1'b0, isSignedC & MulFirst};
					
assign Cmode[1] = isIdle? isOurAddr & DestAddr[3] & ((~DestAddr[4]&DestAddr[1])|(DestAddr[4]&DestAddr[2])) : isMult;
									
assign Cmode[0] = ~isMult;

assign Sena    = 	isOurAddr & DestAddr[0] | isMult;

assign Busy = isOurAddr & (DestAddr[4:2] != 3'b0_10)&(~isAdd)&(~finished);

always @(posedge clk)
	State <= 	isIdle? 		(Busy? ((DestAddr[3:2] == 2'b11)? sDiv2 : sFirstDiv) : sIdle):
			isDiv2?			sFirstDiv:
			isFirstDiv? 	(isLongCommand? sMult : sAdd):
			(isAdd | finished)?	sIdle : State;
endmodule