Ввод-вывод для быстрого QuatCore

//DestAddr==000x_xxxx : 'OUT'
//DestAddr==001x_xxxx : select output device

//xxxx_xxxx_xxxx_xx00 - UART
//xxxx_xxxx_xxxx_xx01 - LCD
//xxxx_xxxx_xxxx_xx1x - SPI

//also selecting SPI device
//xxxx_xxxx_xxxx_0xxx - Ethernet
//xxxx_xxxx_xxxx_10xx - SD
//xxxx_xxxx_xxxx_11xx - ADC


//IN command is 
//SrcAddr == 1001_0xxx
//(ALU Src was 100x_xxxx, now it is 1000_xxxx)

module QuatCoreIOselector (	input clk, input [7:0] SrcAddr, input [7:0] DestAddr, input [15:0] DataBus, input SPI_busy,
				output UARTtxEN, output LCD_EN, output SPItxEN, output UARTrxEN, output SPIrxEN,
				output reg [1:0] SPIdevice = 2'b0);

parameter enableLCD = 1'b0;
parameter enableUART = 1'b1;
parameter enableSPI = 1'b0;

localparam HasChoice = enableSPI | ((enableLCD + enableUART + enableSPI) > 1);

wire isSelection = (~DestAddr[7]) & (~DestAddr[6]) & DestAddr[5] & HasChoice;
wire isIO_out = (~DestAddr[7])&(~DestAddr[6])&((~DestAddr[5]) | (~HasChoice));
wire isIO_in = (SrcAddr[7:3] == 5'b1001_0);

reg [1:0] sel = enableUART? 	2'b00:
		enableLCD?	2'b01:
				2'b10;

reg [1:0] shadowSPI = 2'b0;

always @(posedge clk) if (isSelection) begin
	sel <= DataBus[1:0];
	shadowSPI <= DataBus[3:2];
end

always @(posedge clk) if (~SPI_busy)
	SPIdevice <= shadowSPI;
	
assign UARTtxEN = (sel==2'b00) & isIO_out & enableUART;
assign LCD_EN = (sel==2'b01) & isIO_out & enableLCD;
assign SPItxEN = sel[1] & isIO_out & enableSPI;

assign UARTrxEN = (sel==2'b00) & isIO_in & enableUART;
assign SPIrxEN = sel[1] & isIO_in & enableSPI;

endmodule

`include "math.v"

module QuatCoreUARTtx (input clk, input st, input [15:0] DataBus, output busy, output txd);

	parameter CLKfreq = 4_000_000;
	parameter BAUDrate = 1_000_000;

	localparam sIdle 	=	4'b0000;
	localparam sStart	=	4'b0110;
	localparam sB1		=	4'b0111;
	localparam sB2		=	4'b1000;
	localparam sB3		=	4'b1001;
	localparam sB4		=	4'b1010;
	localparam sB5		=	4'b1011;
	localparam sB6		=	4'b1100;
	localparam sB7		=	4'b1101;
	localparam sB8		=	4'b1110;
	localparam sStop	= 	4'b1111;

	wire [3:0] State;
	wire isStopState;
	wire isIdle = (~State[3]) & (~State[2]); //shortcut as not all states are used
	
	wire DoStart = st & isIdle;
	wire [7:0] Data = DataBus[7:0];
	wire ce; 	//count enable
	reg r_ce = 1'b0;
	reg r_set = 1'b0;
	always @(posedge clk) begin
		r_ce <= ce;
		r_set <= ce | DoStart | isIdle;
	end
	
	lpm_counter StateMachine (
					.clock (clk),
					.cnt_en (r_ce),
					.sset (DoStart),
					.q (State),
					.cout (isStopState) );
	defparam
		StateMachine.lpm_direction = "UP",
		StateMachine.lpm_port_updown = "PORT_UNUSED",
		StateMachine.lpm_type = "LPM_COUNTER",
		StateMachine.lpm_width = 4,
		StateMachine.lpm_svalue = sStart;

	localparam DividerBits = `CLOG2(((CLKfreq + BAUDrate / 2) / BAUDrate - 1));
	localparam Limit = (CLKfreq + BAUDrate / 2) / BAUDrate - 2;

	lpm_counter Divider (
				.clock (clk),
				.sset (r_set),
				.cout (ce) );
  defparam
    Divider.lpm_direction = "DOWN",
    Divider.lpm_port_updown = "PORT_UNUSED",
    Divider.lpm_type = "LPM_COUNTER",
    Divider.lpm_width = DividerBits,
    Divider.lpm_svalue = Limit;
							
	reg [8:0] ShiftReg = 9'b1111_1111_1;
	assign txd = ShiftReg[0];

	assign busy = st & (~isIdle);

always @(posedge clk) if (DoStart | r_ce)
		ShiftReg <= DoStart? {Data, 1'b0} : {1'b1, ShiftReg[8:1]};

endmodule

module QuatCoreSrcMux (input [15:0] SRAM, input [15:0] MEM, input [15:0] ALU, input [15:0] IMM, input [15:0] PC, input [15:0] IO, input [7:0] SrcAddr, input clk, input stall, output [15:0] Q);

parameter DoLatch = 1'b1;
parameter EnableIO = 1'b0;
parameter EnableSRAM = 1'b0;

reg [15:0] rQ;
wire [15:0] combQ;

assign combQ = (~SrcAddr[7])? 				IMM	:
               SrcAddr[6]? 				MEM	:
               SrcAddr[5]?   				PC	:
               (~SrcAddr[4])|(~(EnableIO|EnableSRAM))?	ALU	:
               (SrcAddr[3]&EnableSRAM)|(~EnableIO)?	SRAM	:
							IO;
                                    
always @(posedge clk) if (~stall)
	rQ <= combQ;
	
assign Q = DoLatch? rQ : combQ;

endmodule