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module QuatCoreFastSRAM (input clk, input [7:0] DestAddr, input [7:0] SrcAddr, input DestStall, input SrcStall, input SrcDiscard, input [15:0] D,
			input ReadEnable, input WriteFromADC, input [7:0] GPU,
			output [18:0] RAMaddr, output RAM_CE0, output RAM_CE1, output RAM_RW,
			inout [7:0] RAM_data);
						
wire IsOurDest = (~DestStall)&(~DestAddr[7])&DestAddr[6]&(~DestAddr[5]);
wire IsOurSrc = (~SrcStall)&(~SrcDiscard)&(SrcAddr[7:3] == 5'b1001_1)&ReadEnable;

wire LoadERL = IsOurDest & (~DestAddr[4]) & (~DestAddr[3]);
wire LoadERH = IsOurDest & (~DestAddr[4]) & DestAddr[3];
wire WriteMem = IsOurDest & DestAddr[4];

wire DoWriteFromADC = WriteFromADC & (~ReadEnable);

wire DoIncrement = WriteMem | IsOurSrc | DoWriteFromADC ;

wire [19:0] ER; //External memory Register
wire TC; //Terminal Count

lpm_counter ERL (.clock (clk),
		.cnt_en (DoIncrement),
		.sload (LoadERL),
		.data (D),
		.Q (ER[15:0]),
		.cout (TC));
defparam
	ERL.lpm_direction = "UP",
	ERL.lpm_port_updown = "PORT_UNUSED",
	ERL.lpm_type = "LPM_COUNTER",
	ERL.lpm_width = 16;
	
lpm_counter ERH (.clock (clk),
		.cnt_en (TC & DoIncrement),
		.sload (LoadERH),
		.data (D[3:0]),
		.Q (ER[19:16]));
defparam
	ERH.lpm_direction = "UP",
	ERH.lpm_port_updown = "PORT_UNUSED",
	ERH.lpm_type = "LPM_COUNTER",
	ERH.lpm_width = 4;
	
assign RAMaddr = ER[19:1];
assign RAM_CE0 = ~(ER[0]&(ReadEnable | WriteMem | DoWriteFromADC));
assign RAM_CE1 = ~(~ER[0]&(ReadEnable | WriteMem | DoWriteFromADC));
assign RAM_RW = ((~WriteMem) & (~DoWriteFromADC)) | clk;

assign RAM_data = ReadEnable? (WriteMem? D[7:0] : 8'bzzzz_zzzz) : GPU[7:0];
//(WriteMem & ReadEnable)? D[7:0] : 8'bzzzz_zzzz;

endmodule

module QuatCoreCVinterruptEncoder (input clk, input OFLO, input UFLO, input WDT, output StallEn, output reg NMI=1'b0, output reg [1:0] intN = 2'b00);

parameter EnableNMI = 1'b1;

wire wNMI = OFLO | UFLO | WDT;
reg rNMI = 1'b0;

always @(posedge clk) begin
	rNMI <= wNMI;
	NMI <= (wNMI & (~rNMI)) & EnableNMI;
	intN <= WDT? 	2'b00:
		OFLO?	2'b01:
			2'b10;
end

assign StallEn = ~NMI;

endmodule